Performance of RAID5 disk arrays with read and write caching
Distributed and Parallel Databases - Special issue on disk arrays
An Efficient NAND Flash File System for Flash Memory Storage
IEEE Transactions on Computers
Formalising Flash Memory: First Steps
ICECCS '07 Proceedings of the 12th IEEE International Conference on Engineering Complex Computer Systems
Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design
Proceedings of the 44th annual Design Automation Conference
The five-minute rule twenty years later, and how flash memory changes the rules
DaMoN '07 Proceedings of the 3rd international workshop on Data management on new hardware
Proceedings of the 2008 ACM symposium on Applied computing
The Behavior Analysis of Flash-Memory Storage Systems
ISORC '08 Proceedings of the 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing
A case for flash memory ssd in enterprise database applications
Proceedings of the 2008 ACM SIGMOD international conference on Management of data
A Hybrid Flash File System Based on NOR and NAND Flash Memories for Embedded Devices
IEEE Transactions on Computers
A Reliability Enhancing Mechanism for a Large Flash Embedded Satellite Storage System
ICONS '08 Proceedings of the Third International Conference on Systems
Response time distribution of flash memory accesses
Proceedings of the 3rd International Conference on Performance Evaluation Methodologies and Tools
Abstract Specification of the UBIFS File System for Flash Memory
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Response time distribution of flash memory accesses
Performance Evaluation
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The impact of wear levelling on a Flash storage package and its access operations' execution modes is investigated. First, a simple, static logical-to-physical mapping function is proposed and its implied wear levelling is assessed for different distributions of addresses, covering both uniform access and hotspots, as well as the Flash chip utilization within the whole package. Second, for each access mode, different preemptive and non-preemptive priority schemes are considered with a range of IO arrival rates, using Poisson-, Erlang- and Pareto-based arrival processes. The analysis of the impact of the execution modes on the performance of the Flash memory is undertaken using a hardware simulator. The results show clearly the good wear levelling obtained by the mapping functions, even in the presence of hotspots. In addition, the impact of the chosen execution mode on the whole storage package for each IO workload type is assessed, both qualitatively and quantitatively.