A caching-oriented management design for the performance enhancement of solid-state drives
ACM Transactions on Storage (TOS)
Hybrid nonvolatile disk cache for energy-efficient and high-performance systems
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
ACM Transactions on Storage (TOS)
Random data-aware flash translation layer for NAND flash-based smart devices
The Journal of Supercomputing
| Hi-index | 14.98 |
Cost has been a major driving force in the development of the flash-memory technology. Because of this, serious challenges are now faced for future products on reliability and performance requirements. In this work, we propose a management strategy to resolve the reliability and performance problems of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of advanced multilevel cell flash-memory chips. The capability of the proposed approach is analyzed with reliability considerations and evaluated by experiments over realistic workloads with respect to the reliability and performance improvement.