Algorithms and data structures for flash memories
ACM Computing Surveys (CSUR)
Efficient identification of hot data for flash memory storage systems
ACM Transactions on Storage (TOS)
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
LAST: locality-aware sector translation for NAND flash memory-based storage systems
ACM SIGOPS Operating Systems Review
Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
A survey of Flash Translation Layer
Journal of Systems Architecture: the EUROMICRO Journal
Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme
ACM Transactions on Embedded Computing Systems (TECS)
A set-based mapping strategy for flash-memory reliability enhancement
Proceedings of the Conference on Design, Automation and Test in Europe
KAST: K-Associative Sector Translation for NAND flash memory in real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
A Hybrid Approach to NAND-Flash-Based Solid-State Disks
IEEE Transactions on Computers
IEEE Transactions on Computers
A study on the block fragmentation problem of ssd based on NAND flash memory
Proceedings of the 5th International Conference on Ubiquitous Information Management and Communication
Sector log: fine-grained storage management for solid state drives
Proceedings of the 2011 ACM Symposium on Applied Computing
Proceedings of the international conference on Supercomputing
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
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Flash memory is used widely in the data storage market, particularly low-price MultiLevel Cell (MLC) flash memory, which has been adopted by large-scale storage systems despite its low performance. To overcome the poor performance of MLC flash memory, a system architecture has been designed to optimize chip-level parallelism. This design increases the size of the page unit and the block unit, thereby simultaneously executing operations on multiple chips. Unfortunately, its Flash Translation Layer (FTL) generates many unused sectors in each page, which leads to unnecessary write operations. Furthermore, it reuses an earlier log block scheme, although it generates many erase operations because of its low space utilization. To solve these problems, we propose a hybrid associative FTL (Hybrid-FTL) to enhance the performance of the chip-level parallel flash memory system. Hybrid-FTL reduces the number of write operations by utilizing all of the unused sectors. Furthermore, it reduces the overall number of erase operations by classifying data as hot, cold, or fragment data. Hybrid-FTL requires less mapping information in the DRAM and in the flash memory compared with previous FTL algorithms.