A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
FTL design exploration in reconfigurable high-performance SSD for server applications
Proceedings of the 23rd international conference on Supercomputing
KAST: K-Associative Sector Translation for NAND flash memory in real-time systems
Proceedings of the Conference on Design, Automation and Test in Europe
System software for flash memory: a survey
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
ACM Transactions on Storage (TOS)
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A Solid State Disk (SSD) has recently occupied attentions as the next generation of memory media. Among researches of various technologies to increase the performance of the SSD, a parallel method has the most effect on the performance improvement. Thus, the SSD uses logical address striping technique. It contributes to a sharp increase of the feature of being parallel while some mapping methods might cause a problem in the use of block. This paper will verify the issues of changes of a block to fragments caused when the methods of logical address, striping and of hybrid mapping are used at the same time, and analyze impacts of the fragment issue on a block exploitation and ability.