Algorithms and data structures for flash memories
ACM Computing Surveys (CSUR)
CFLRU: a replacement algorithm for flash memory
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
A multi-channel architecture for high-performance NAND flash-based storage system
Journal of Systems Architecture: the EUROMICRO Journal
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
The five-minute rule twenty years later, and how flash memory changes the rules
DaMoN '07 Proceedings of the 3rd international workshop on Data management on new hardware
BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
Queue - Enterprise Flash Storage
Queue - Enterprise Flash Storage
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
FTL design exploration in reconfigurable high-performance SSD for server applications
Proceedings of the 23rd international conference on Supercomputing
Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems
Proceedings of the 36th annual international symposium on Computer architecture
A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Exploiting Internal Parallelism of Flash-based SSDs
IEEE Computer Architecture Letters
Write endurance in flash drives: measurements and analysis
FAST'10 Proceedings of the 8th USENIX conference on File and storage technologies
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation
MSST '10 Proceedings of the 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST)
System software for flash memory: a survey
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
FAB: flash-aware buffer management policy for portable media players
IEEE Transactions on Consumer Electronics
Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices
IEEE Transactions on Consumer Electronics
B+-tree index optimization by exploiting internal parallelism of flash-based solid state drives
Proceedings of the VLDB Endowment
An evaluation of different page allocation strategies on high-speed SSDs
HotStorage'12 Proceedings of the 4th USENIX conference on Hot Topics in Storage and File Systems
SAC: rethinking the cache replacement policy for SSD-based storage systems
Proceedings of the 5th Annual International Systems and Storage Conference
Middleware - firmware cooperation for high-speed solid state drives
Proceedings of the Posters and Demo Track
Revisiting widely held SSD expectations and rethinking system-level implications
Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems
MMSoC: a multi-layer multi-core storage-on-chip design for systems with high integration
Proceedings of the 14th International Conference on Computer Systems and Technologies
Scan and join optimization by exploiting internal parallelism of flash-based solid state drives
WAIM'13 Proceedings of the 14th international conference on Web-Age Information Management
ACM Transactions on Storage (TOS)
Triple-A: a Non-SSD based autonomic all-flash array for high performance storage systems
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
BLAS: Block-level adaptive striping for solid-state drives
ACM Transactions on Design Automation of Electronic Systems (TODAES)
LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives
FAST'13 Proceedings of the 11th USENIX conference on File and Storage Technologies
Flashmon V2: monitoring raw NAND flash memory I/O requests on embedded Linux
ACM SIGBED Review - Special Issue on the 3rd Embedded Operating System Workshop (EWiLi 2013)
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With the development of the NAND-Flash technology, NAND-Flash based Solid-State Disk (SSD) has been attracting a great deal of attention from both industry and academia. While a range of SSD research topics, from interface techniques to buffer management and Flash Translation Layer (FTL), from performance to endurance and energy efficiency, have been extensively studied in the literature, the SSD being studied was by and large treated as a grey or black box in that many of the internal features such as advanced commands, physical-page allocation schemes and data granularity are hidden or assumed away. We argue that, based on our experimental study, it is these internal features and their interplay that will help provide the missing but significant insights to designing high-performance and high-endurance SSDs. In this paper, we use our highly accurate and multi-tiered SSD simulator, called SSDsim, to analyze several key internal SSD factors to characterize their performance impacts, interplay and parallelisms for the purpose of performance and endurance en-hancement of SSDs. From the results of our experiments, we found that: (1) larger pages tend to have significantly negative impact on SSD performance under many workloads; (2) different physical-page allocation schemes have different deployment en-vironments, where an optimal allocation scheme can be found for each workload; (3) although advanced commands provided by flash manufacturers can improve performance in some cases, they may jeopardize the SSD performance and endurance when used inappropriately; (4) since the parallelisms of SSD can be classified into four levels, namely, channel-level, chip-level, die-level and plane-level, the priority order of SSD parallelism, resulting from the strong interplay among physical-page allocation schemes and advanced commands, can have a very significant impact on SSD performance and endurance.