Cleaning policies in mobile computers using flash memory
Journal of Systems and Software
An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
An adaptive two-level management for the flash translation layer in embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A multi-channel architecture for high-performance NAND flash-based storage system
Journal of Systems Architecture: the EUROMICRO Journal
BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
A reconfigurable FTL (flash translation layer) architecture for NAND flash-based applications
ACM Transactions on Embedded Computing Systems (TECS)
LAST: locality-aware sector translation for NAND flash memory-based storage systems
ACM SIGOPS Operating Systems Review
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
FTL design exploration in reconfigurable high-performance SSD for server applications
Proceedings of the 23rd international conference on Supercomputing
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A self-adjusting flash translation layer for resource-limited embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme
ACM Transactions on Embedded Computing Systems (TECS)
Buffer flush and address mapping scheme for flash memory solid-state disk
Journal of Systems Architecture: the EUROMICRO Journal
Exploiting Internal Parallelism of Flash-based SSDs
IEEE Computer Architecture Letters
Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture
IEEE Transactions on Computers
BPAC: An adaptive write buffer management scheme for flash-based Solid State Drives
MSST '10 Proceedings of the 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST)
ROSE: A Novel Flash Translation Layer for NAND Flash Memory Based on Hybrid Address Translation
IEEE Transactions on Computers
CAVE: channel-aware buffer management scheme for solid state disk
Proceedings of the 2011 ACM Symposium on Applied Computing
Proceedings of the international conference on Supercomputing
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
A Pattern Adaptive NAND Flash Memory Storage Structure
IEEE Transactions on Computers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cross-Layer Optimizations in Solid-State Drives
IEEE Embedded Systems Letters
DuLASP: A Workload-Aware Flash Translation Layer Exploiting both Temporal and Spatial Localities
RTCSA '12 Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Active flash: towards energy-efficient, in-situ data analytics on extreme-scale machines
FAST'13 Proceedings of the 11th USENIX conference on File and Storage Technologies
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Increasing the degree of parallelism and reducing the overhead of garbage collection (GC overhead) are the two keys to enhancing the performance of solid-state drives (SSDs). SSDs employ multichannel architectures, and a data placement scheme in an SSD determines how the data are striped to the channels. Without considering the data access pattern, existing fixed and device-level data placement schemes may have either high GC overhead or poor I/O parallelism, resulting in degraded performance. In this article, an adaptive block-level data placement scheme called BLAS is proposed to maximize the I/O parallelism while simultaneously minimizing the GC overhead. In contrast to existing device-level schemes, BLAS allows different data placement policies for blocks with different access patterns. Pages in read-intensive blocks are scattered over various channels to maximize the degree of read parallelism, while pages in each of the remaining blocks are attempted to be gathered in the same physical block to minimize the GC overhead. Moreover, BLAS allows the placement policy for a logical block to be changed dynamically according to the access pattern changes of that block. Finally, a parallelism-aware write buffer management approach is adopted in BLAS to maximize the degree of write parallelism. Performance results show that BLAS yields a significant improvement in the SSD response time when compared to existing device-level schemes. In particular, BLAS outperforms device-level page striping and device-level block striping by factors of up to 8.75 and 7.41, respectively. Moreover, BLAS achieves low GC overhead and is effective in adapting to workload changes.