CFLRU: a replacement algorithm for flash memory
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
A multi-channel architecture for high-performance NAND flash-based storage system
Journal of Systems Architecture: the EUROMICRO Journal
A log buffer-based flash translation layer using fully-associative sector translation
ACM Transactions on Embedded Computing Systems (TECS)
BPLRU: a buffer management scheme for improving random writes in flash storage
FAST'08 Proceedings of the 6th USENIX Conference on File and Storage Technologies
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
μ-FTL:: a memory-efficient flash translation layer supporting multiple mapping granularities
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
LAST: locality-aware sector translation for NAND flash memory-based storage systems
ACM SIGOPS Operating Systems Review
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
IEEE Transactions on Computers
A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture
IEEE Transactions on Computers
STOW: a spatially and temporally optimized write caching algorithm
USENIX'09 Proceedings of the 2009 conference on USENIX Annual technical conference
A space-efficient flash translation layer for CompactFlash systems
IEEE Transactions on Consumer Electronics
FAB: flash-aware buffer management policy for portable media players
IEEE Transactions on Consumer Electronics
Recently-evicted-first buffer replacement policy for flash storage devices
IEEE Transactions on Consumer Electronics
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
BLAS: Block-level adaptive striping for solid-state drives
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
Exploiting a multi-channel architecture of Solid State Disk (SSD) is a role of Flash Translation Layer (FTL) until now. A multi-channel FTL scheme increases I/O parallelism by spreading out pages in a logical block to multiple channels. However, this scheme has high garbage collection overhead for reclaiming invalid pages, thus resulting in the performance degradation. In order to overcome this problem, we assign a write buffer to exploit a multi-channel architecture. In this paper, we propose a novel buffer management scheme, called Channel-Aware Victim Eviction (CAVE). The key idea of the CAVE scheme is to evict multiple victims whose number is equal to the number of NAND flash memories when a write buffer is full for increasing I/O parallelism. Because a write buffer exploits a multi-channel architecture, we can use a 1-channel FTL scheme, thus reducing garbage collection overhead. We develop a trace-driven simulator for evaluating the CAVE scheme. The hit ratio and execution time are used as performance metrics. In the hit ratio, the CAVE scheme can achieve a similar result with a conventional method which uses a multi-channel FTL scheme though it evicts more victims at a time. In the execution time which consists of the write time and garbage collection time, a result shows that the CAVE scheme can reduce it by 55.5% - 97.4% in block-level LRU using SYSMARK compared to the conventional method.