A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks

  • Authors:

  • Jinho Seol;Hyotaek Shim;Jaegeuk Kim;Seungryoul Maeng

  • Affiliations:

  • Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea;Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea;Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea;Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea

  • Venue:
  • CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
  • Year:
  • 2009

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Abstract

Solid State Disks (SSDs) are superior to magnetic disks from a performance point of view due to the favorable features of NAND flash memory. Furthermore, thanks to improvement on flash memory density and adopting a multi-chip architecture, SSDs replace magnetic disks rapidly. Most previous studies have been conducted for enhancing the performance of SSDs, but these studies have been worked on the assumption that the operation unit of a host interface is the same as the operation unit of NAND flash memory, where it is needless to give consideration to partially-filled pages. In this paper, we analyze the overhead caused by the partially-filled pages, and propose a buffer replacement algorithm exploiting multi-chip parallelism to enhance the write performance. Our simulation results show that the proposed algorithm improves the write performance by up to 30% over existing approaches.