Hybrid solid-state disks: combining heterogeneous NAND flash in large SSDs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A self-balancing striping scheme for NAND-flash storage systems
Proceedings of the 2008 ACM symposium on Applied computing
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
FRA: a flash-aware redundancy array of flash storage devices
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Delayed partial parity scheme for reliable and high-performance flash memory SSD
MSST '10 Proceedings of the 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST)
Enhancing SSD reliability through efficient RAID support
Proceedings of the Asia-Pacific Workshop on Systems
Enhancing SSD reliability through efficient RAID support
APSys'12 Proceedings of the Third ACM SIGOPS Asia-Pacific conference on Systems
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems
Proceedings of the Conference on Design, Automation and Test in Europe
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Due to the ever-growing capacity of flash memory along with its good properties such as low-power consumption and high performance, flash-based SSDs (solid state disks) are anticipated to be used in the storage of high-end server systems. However, the reliability problem of flash devices is becoming increasingly serious. The number of P/E (program/erase) cycles allowed to each flash block is too small, especially less than 10,000 for MLC (multi-level cell) flash memory. Furthermore, the bit error rate of flash memory becomes rapidly high as the number of P/E cycles increases. To relieve these problems, we present a lifespan-aware reliability scheme, which adopts RAID technologies together with ECCs (error correction codes). First, our scheme dynamically manages the size of striping group to cope with the increasing error rates of flash memory as the number of P/E cycles increases. Second, we use a device-aware log block mapping scheme, which uses different reliability policies for data blocks and log blocks by taking advantage of the characteristics of each block type. Third, we use small amount of storage class memory (SCM) to save parity blocks temporarily. By absorbing frequent updates of parity into SCM, we can extend the lifespan of flash memory. Simulation experiments show that our scheme obtains high reliability with minimum space overhead as well as improved I/O performances compared to traditional RAID-5.