FRA: a flash-aware redundancy array of flash storage devices
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Write activity reduction on flash main memory via smart victim cache
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Flash-Aware RAID Techniques for Dependable and High-Performance Flash Memory SSD
IEEE Transactions on Computers
Exploiting memory device wear-out dynamics to improve NAND flash memory system performance
FAST'11 Proceedings of the 9th USENIX conference on File and stroage technologies
A lifespan-aware reliability scheme for RAID-based flash storage
Proceedings of the 2011 ACM Symposium on Applied Computing
Cooperating Write Buffer Cache and Virtual Memory Management for Flash Memory Based Systems
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
Emerging non-volatile memories: opportunities and challenges
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems
RTSS '11 Proceedings of the 2011 IEEE 32nd Real-Time Systems Symposium
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Program disturb, read disturb and retention time limit are three major reasons accounting for the bit errors in NAND flash memory. The adoption of multi-level cell (MLC) technology and technology scaling further aggravates this reliability issue by narrowing threshold voltage noise margins and introducing larger device variations. Besides implementing error correction code (ECC) in NAND flash modules, RAID-5 are often deployed at system level to protect the data integrity of NAND flash storage systems (NFSS), however, with significant performance degradation. In this work, we propose a technique called "DA-RAID-5" to improve the performance of the enterprise NFSS under RAID-5 protection without harming its reliability (here DA stands for "disturb aware"). Three schemes, namely, unbound-disturb limiting (UDL), PE-aware RAID-5 and Hybrid Caching(HC) are proposed to protect the NFSS at the different stages of its lifetime. The experimental results show that compared to the best prior work, DA-RAID-5 can improve the NFSS response time by 9.7% on average.