WeLe-RAID: a SSD-based RAID for system endurance and performance
NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing
HPDA: A hybrid parity-based disk array for enhanced performance and reliability
ACM Transactions on Storage (TOS)
Enhancing SSD reliability through efficient RAID support
Proceedings of the Asia-Pacific Workshop on Systems
Enhancing SSD reliability through efficient RAID support
APSys'12 Proceedings of the Third ACM SIGOPS Asia-Pacific conference on Systems
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling the aging process of flash storage by leveraging semantic I/O
Future Generation Computer Systems
| Hi-index | 14.98 |
Solid-state disks (SSDs), which are composed of multiple NAND flash chips, are replacing hard disk drives (HDDs) in the mass storage market. The performances of SSDs are increasing due to the exploitation of parallel I/O architectures. However, reliability remains as a critical issue when designing a large-scale flash storage. For both high performance and reliability, Redundant Arrays of Inexpensive Disks (RAID) storage architecture is essential to flash memory SSD. However, the parity handling overhead for reliable storage is significant. We propose a novel RAID technique for flash memory SSD for reducing the parity updating cost. To reduce the number of write operations for the parity updates, the proposed scheme delays the parity update which must accompany each data write in the original RAID technique. In addition, by exploiting the characteristics of flash memory, the proposed scheme uses the partial parity technique to reduce the number of read operations required to calculate a parity. We evaluated the performance improvements using a RAID-5 SSD simulator. The proposed techniques improved the performance of the RAID-5 SSD by 47 percent and 38 percent on average in comparison to the original RAID-5 technique and the previous delayed parity updating technique, respectively.