Scheduling algorithms for modern disk drives
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Cleaning policies in mobile computers using flash memory
Journal of Systems and Software
An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems
RTAS '02 Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'02)
Real-time garbage collection for flash-memory storage systems of real-time embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Algorithms and data structures for flash memories
ACM Computing Surveys (CSUR)
Current trends in flash memory technology: invited paper
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A flash-memory based file system
TCON'95 Proceedings of the USENIX 1995 Technical Conference Proceedings
Competitive analysis of flash-memory algorithms
ESA'06 Proceedings of the 14th conference on Annual European Symposium - Volume 14
A self-balancing striping scheme for NAND-flash storage systems
Proceedings of the 2008 ACM symposium on Applied computing
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
Proceedings of the 36th annual international symposium on Computer architecture
Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture
IEEE Transactions on Computers
Built-in self-repair schemes for flash memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
How i learned to stop worrying and love flash endurance
HotStorage'10 Proceedings of the 2nd USENIX conference on Hot topics in storage and file systems
Optimizing NAND flash-based SSDs via retention relaxation
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Lifetime management of flash-based SSDs using recovery-aware dynamic throttling
FAST'12 Proceedings of the 10th USENIX conference on File and Storage Technologies
Estimating MLC NAND flash endurance: a genetic programming based symbolic regression application
Proceedings of the 15th annual conference on Genetic and evolutionary computation
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems
Proceedings of the Conference on Design, Automation and Test in Europe
Extending SSD lifetime in database applications with page overwrites
Proceedings of the 6th International Systems and Storage Conference
Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.00 |
This paper advocates a device-aware design strategy to improve various NAND flash memory system performance metrics. It is well known that NAND flash memory program/erase (PE) cycling gradually degrades memory device raw storage reliability, and sufficiently strong error correction codes (ECC) must be used to ensure the PE cycling endurance. Hence, memory manufacturers must fabricate enough number of redundant memory cells geared to the worst-case device reliability at the end of memory lifetime. Given the memory device wear-out dynamics, the existing worst-case oriented ECC redundancy is largely under-utilized over the entire memory lifetime, which can be adaptively traded for improving certain NAND flash memory system performance metrics. This paper explores such device-aware adaptive system design space from two perspectives, including (1) how to improve memory program speed, and (2) how to improve memory defect tolerance and hence enable aggressive fabrication technology scaling. To enable quantitative evaluation, we for the first time develop a NAND flash memory device model to capture the effects of PE cycling from the system level. We carry out simulations using the DiskSim-based SSD simulator and a variety of traces, and the results demonstrate up to 32% SSD average response time reduction. We further demonstrate that the potential on achieving very good defect tolerance, and finally show that these two design approaches can be readily combined together to noticeably improve SSD average response time even in the presence of high memory defect rates.