Error Correction Coding: Mathematical Methods and Algorithms
Error Correction Coding: Mathematical Methods and Algorithms
Memory mapped ECC: low-cost error protection for last level caches
Proceedings of the 36th annual international symposium on Computer architecture
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
Proceedings of the 46th Annual Design Automation Conference
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
Error-correcting codes for semiconductor memory applications: a state-of-the-art review
IBM Journal of Research and Development
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
Exploiting memory device wear-out dynamics to improve NAND flash memory system performance
FAST'11 Proceedings of the 9th USENIX conference on File and stroage technologies
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The STeTSiMS STT-RAM simulation and modeling system
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Proceedings of the 49th Annual Design Automation Conference
A Statistical Model for Indoor Multipath Propagation
IEEE Journal on Selected Areas in Communications
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches
Proceedings of the International Conference on Computer-Aided Design
Multi-level cell STT-RAM: is it realistic or just a dream?
Proceedings of the International Conference on Computer-Aided Design
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies
Asymmetry of MTJ switching and its implication to STT-RAM designs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The write operation asymmetry of many memory technologies causes different write failure rates at 0 → 1 and 1 → 0 bit-flipping's. Conventional error correction codes (ECCs) spend the same efforts on both bit-flipping directions, leading to very unbalanced write reliability enchantment over different bit-flipping distributions of codewords (i.e., the number of 0 → 1 or 1 → 0 bit-flipping's). In this work, we developed an analytic asymmetric write channel (AWC) model to analyze the asymmetric write errors in spin-transfer torque random access memory (STT-RAM) designs. A new ECC design concept, namely, content-dependent ECC (CD-ECC), is proposed to achieve balanced error correction at both bit-flipping directions. Two CD-ECC schemes -- typical-corner-ECC (TCE) and worst-corner-ECC (WCE), are designed for the codewords with different bit-flipping distributions. Our simulation results show that compared to the common ECC schemes utilized in embedded applications like Hamming code, CD-ECCs can improve the STT-RAM write reliability by 10--30x with low hardware overhead and very marginal impact on system performance.