Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Challenges in Embedded Memory Design and Test
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
The zen of nonvolatile memories
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search speed
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design techniques to improve the device write margin for MRAM-based cache memory
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
Proceedings of the International Conference on Computer-Aided Design
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 49th Annual Design Automation Conference
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Proceedings of the 49th Annual Design Automation Conference
A dual-mode architecture for fast-switching STT-RAM
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Process variation aware data management for STT-RAM cache design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches
Proceedings of the International Conference on Computer-Aided Design
OAP: an obstruction-aware cache management policy for STT-RAM last-level caches
Proceedings of the Conference on Design, Automation and Test in Europe
STT-RAM designs supporting dual-port accesses
Proceedings of the Conference on Design, Automation and Test in Europe
Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asymmetry of MTJ switching and its implication to STT-RAM designs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the International Conference on Computer-Aided Design
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications
Proceedings of the International Conference on Computer-Aided Design
Unleashing the potential of MLC STT-RAM caches
Proceedings of the International Conference on Computer-Aided Design
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Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors. Due to unique operational characteristics of its storage device magnetic tunneling junction (MTJ), STT RAM is inherently subject to a write latency versus read latency tradeoff that is determined by the memory cell size. This paper first quantitatively studies how different memory cell sizing may impact the overall computing system performance, and shows that different computing workloads may have conflicting expectations on memory cell sizing. Leveraging MTJ device switching characteristics, we further propose an STT RAM architecture design method that can make STT RAM cache with relatively small memory cell size perform well over a wide spectrum of computing benchmarks. This has been well demonstrated using CACTI-based memory modeling and computing system performance simulations using SimpleScalar. Moreover, we show that this design method can also reduce STT RAM cache energy consumption by up to 30% over a variety of benchmarks.