Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Progress and outlook for STT-MRAM
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Proceedings of the 49th Annual Design Automation Conference
Asymmetry of MTJ switching and its implication to STT-RAM designs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Layout-aware optimization of STT MRAMs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Spin-transfer torque random access memory (STT-RAM) is an emerging non-volatile memory technology offering many attractive characteristics like high integration density, nanosecond access time, and good CMOS compatibility. However, the performance and reliability of STT-RAM cells are greatly affected by process variations and intrinsic device operation randomness. In this work, we proposed a novel STT-RAM cell structure named ADAMS which can be dynamically configured between the high-reliable (HR) mode and the high-capacity (HC) mode upon the real-time system requirement: For the performance and reliability critical applications, ADAMS switches to HR mode. The novel connection scheme of magnetic tunneling junction (MTJ) devices and programming/sensing circuits substantially improve the read and write performance of the ADAMS cell and enhance its resilience to operation errors; For the capacity critical applications, ADAMS switches to HC mode. The ADAMS cell is broken into two "1T1J" cells that can work independently, offering the similar performance and reliability to conventional STT-RAM design. Simulation results show that compared to convectional 1T1J cell structure, ADAMS offers the same write latency, smaller cell area, and 12× lower write error rate. The read latency is also improved by 44.2% with 1935.8× reduction on combined read error rate.