Review of fuse and antifuse solutions for advanced standard CMOS technologies
Microelectronics Journal
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Silicon technology based nonvolatile memories (NVM) have achieved widespread adoption for code and data storage applications. In the last 30 years, the traditional oating gate bitcell has been scaled following Moore's law, but recently scaling limits have been encountered which will require alternative solutions after the 65 nm technology node. Both evolutionary and novel solutions are being pursued in the industry. While the traditional oating gate technology will scale to the 65 nm node, novel device structures and array architectures will be needed past that node.