Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
Proceedings of the 46th Annual Design Automation Conference
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search speed
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)
Proceedings of the Conference on Design, Automation and Test in Europe
Emerging sensing techniques for emerging memories
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Universal statistical cure for predicting memory loss
Proceedings of the International Conference on Computer-Aided Design
Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Electrothermal analysis of spin-transfer-torque random access memory arrays
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies
SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors
Proceedings of the Conference on Design, Automation and Test in Europe
Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asymmetry of MTJ switching and its implication to STT-RAM designs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
We proposed a combined magnetic and circuit level technique to explore the design methodology of Spin-Torque Transfer RAM (SPRAM). A dynamic magnetic model of magnetic tunneling junction (MTJ), which is based upon measured spin torque induced magnetization switching behavior, is also proposed. The response of CMOS circuitry is characterized by SPICE and used as the input of our MTJ model to simulate the dynamic behavior of SPRAM cell. By using this technique, we explored the design margin of SPRAM cell with one-transistor-one-MTJ (1T1J) structure. Simulation results show that our technique can significantly reduce the design pessimism, compared to conventional SRPAM cell model.