Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A resistive TCAM accelerator for data-intensive computing
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
AC-DIMM: associative computing with STT-MRAM
Proceedings of the 40th Annual International Symposium on Computer Architecture
A magnetic tunnel junction based zero standby leakage current retention flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring the use of emerging nonvolatile memory technologies in future FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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With a great scalability potential, nonvolatile magnetoresistive memory with spin-torque transfer (STT) programming has become a topic of great current interest. This paper addresses cell structure design for STT magnetoresistive RAM, content addressable memory (CAM) and ternary CAM (TCAM). We propose a new RAM cell structure design that can realize high speed and reliable sensing operations in the presence of relatively poor magnetoresistive ratio, while maintaining low sensing current through magnetic tunneling junctions (MTJs). We further apply the same basic design principle to develop new cell structures for nonvolatile CAM, and TCAM. The effectiveness of the proposed RAM, CAM and TCAM cell structures has been demonstrated by circuit simulation at 0.18 µm CMOS technology.