Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A hybrid Nano/CMOS dynamically reconfigurable system—Part II: Design optimization flow
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search speed
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA
IEEE Transactions on Nanotechnology
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As new nonvolatile memory technologies become increasingly mature, there has been a growing interest on investigating their use in future field-programmable gate arrays (FPGAs). Similar to existing FPGAs with embedded Flash memory, future FPGAs can embed these new nonvolatile memories to persistently store configuration data. By comparing with prior work, we first propose the more appropriate design style for new nonvolatile configuration data storage memory. Moreover, this brief studies a dynamic random-access memory (DRAM)- based FPGA design strategy enabled by high-density embedded nonvolatile memory. Existing FPGAs do not use on-chip DRAM cells for configuration data storage mainly because DRAM self-refresh involves destructive DRAM read. This problem can be solved, if we use embedded nonvolatile memory as primary FPGA configuration data storage and externally refresh on-chip DRAM cells. Analysis and simulations have been carried out to demonstrate the potential advantages of such a design strategy.