Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A new hybrid FPGA with nanoscale clusters and CMOS routing
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Variability-Tolerant Register-Transfer Level Synthesis
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Hierarchical test generation and design for testability methods for ASPPs and ASIPs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect-aware low-power high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
SRAM-based NATURE: a dynamically reconfigurable FPGA based on 10T low-power SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring the use of emerging nonvolatile memory technologies in future FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
In Part I of this work, a hybrid nano/CMOS reconfigurable architecture, called NATURE, was described. It is composed of CMOS reconfigurable logic and interconnect fabric, and nonvolatile nano on-chip memory. Through its support for cycle-by-cycle runtime reconfiguration and a highly-efficient computation model, temporal logic folding, NATURE improves logic density and area-delay product by more than an order of magnitude compared to existing CMOS-based field-programmable gate arrays (FPGAs). NATURE can be fabricated using mainstream photo-lithography fabrication techniques. Thus, it offers a currently commercially feasible architecture with high performance, superior logic density, and excellent runtime design flexibility. In Part II of this work, we present an integrated design and optimization flow for NATURE, called NanoMap. Given an input design specified in register-transfer level (RTL) and/or gate-level VHDL, NanoMap optimizes and implements the design on NATURE through logic mapping, temporal clustering, temporal placement, and routing. As opposed to other design tools for traditional FPGAs, NanoMap supports and leverages temporal logic folding by integrating novel mapping techniques. It can automatically explore and identify the best temporal logic folding configuration, targeting area, delay or area-delay product optimization. A force-directed scheduling technique is used to optimize and balance resource usage across different folding cycles. By supporting logic folding, NanoMap can provide significant design flexibility in performing area-delay trade-offs under various user-specified constraints. We present details of the mapping procedure and results for different architectural instances. Experimental results demonstrate that NanoMap can judiciously trade off area and delay targeting different optimization goals, and effectively exploit the advantages of NATURE. Part I of this work will appear in JETC Vol. 5, No. 4.