Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Exploring technology alternatives for nano-scale FPGA interconnects
Proceedings of the 42nd annual Design Automation Conference
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Fine-grained island style architecture for molecular electronic devices
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SCT: A novel approach for testing and configuring nanoscale devices
ACM Journal on Emerging Technologies in Computing Systems (JETC)
FPCNA: a field programmable carbon nanotube array
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A hybrid Nano/CMOS dynamically reconfigurable system—Part II: Design optimization flow
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A hybrid nano-CMOS architecture for defect and fault tolerance
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions
Proceedings of the 46th Annual Design Automation Conference
Design and evaluation of a carbon nanotube-based programmable architecture
International Journal of Parallel Programming
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of nanowires configured to implement the required LUTs and intra-cluster MUXes. A CMOS interface is also proposed to provide configuration and latching for the nanoscale cluster. Inter-cluster routing is assumed to remain at CMOS scale. Experimental analysis is performed to evaluate area and performance of the hybrid FPGA and results are compared with traditional fully CMOS FPGA (scaled to 22nm). Up to 75% area reduction was obtained from implementing MCNC benchmarks on hybrid FPGA. Performance of the hybrid FPGA is shown to be close to that of CMOS FPGA.