NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Defect tolerance on the Teramac custom computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Built-In Self-Test of Molecular Electronics-Based Nanofabrics
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
CAEN-BIST: Testing the NanoFabric
ITC '04 Proceedings of the International Test Conference on International Test Conference
Application-Dependent Diagnosis of FPGAs
ITC '04 Proceedings of the International Test Conference on International Test Conference
Fine-grained island style architecture for molecular electronic devices
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A new hybrid FPGA with nanoscale clusters and CMOS routing
Proceedings of the 43rd annual Design Automation Conference
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Novel strategies are necessary to efficiently test and configure emerging reconfigurable nanoscale devices, in addition to providing defect tolerance. This is mainly due to the high defect densities that are expected for these devices. Among different approaches, reconfiguration-based defect avoidance has proven to be a practical solution. However, configuration time, test time, and defect-map size remain among the major challenges for these new devices. In this article, we propose a new approach (called SCT) that simultaneously performs test and configuration. The proposed method uses a built-in self-test (BIST) scheme for test and defect tolerance. The method is based on testing reconfigurable nanoblocks at the time of implementing a function of a desired application on that block. The SCT method considerably reduces the total test and configuration time. It also eliminates the need for storing the location of defects in a defect map on- or off-chip. The presented probabilistic analysis results show the effectiveness of this method in terms of test and configuration time for architectures with rich interconnect resources. Also, a Verilog simulation model is developed for crossbar-based nano-architectures. This model is used to implement several MCNC benchmarks based on the proposed SCT method. The simulation results demonstrate efficiency of the method in terms of test time and yield under different defect rates.