Built-In Self-Test of Molecular Electronics-Based Nanofabrics

Authors:
Zhanglei Wang;Krishnendu Chakrabarty
Affiliations:
Duke University;Duke University
Venue:
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Year:
2005

Citing 0
Cited 6

A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology

Journal of Electronic Testing: Theory and Applications
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics

Journal of Electronic Testing: Theory and Applications
Bilateral Testing of Nano-scale Fault-Tolerant Circuits

Journal of Electronic Testing: Theory and Applications
SCT: A novel approach for testing and configuring nanoscale devices

ACM Journal on Emerging Technologies in Computing Systems (JETC)
BISM: built-in self map for hybrid crossbar nano-architectures

Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low-overhead defect tolerance in crossbar nanoarchitectures

ACM Journal on Emerging Technologies in Computing Systems (JETC)

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Abstract

An unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. ...