Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Electrical testing for failure analysis: E-beam testing
Proceedings of the third session on Reliability in VLSI circuits : operation, manufacturing and design: operation, manufacturing and design
Novel technique for testing FPGAs
Proceedings of the conference on Design, automation and test in Europe
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
BIST-Based Diagnostics of FPGA Logic Blocks
Proceedings of the IEEE International Test Conference
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Defect tolerance on the Teramac custom computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Built-In Self-Test of Molecular Electronics-Based Nanofabrics
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
CAEN-BIST: Testing the NanoFabric
ITC '04 Proceedings of the International Test Conference on International Test Conference
SCT: An Approach For Testing and Configuring Nanoscale Devices
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Maintaining the benefits of CMOS scaling when scaling bogs down
IBM Journal of Research and Development
Techniques and algorithms for fault grading of FPGA interconnect test configurations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Nanoarray architectures multilevel simulation
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
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We propose a built-in self-test (BIST) procedure for nanofabrics implemented using chemically assembled electronic nanotechnology. Several fault detection configurations are presented to target stuck-at faults, shorts, opens, and connection faults in nanoblocks and switchblocks. The detectability of multiple faults in blocks within the nanofabric is also considered. We present an adaptive recovery procedure through which we can identify defect-free nanoblocks and switchblocks in the nanofabric-under-test. The proposed BIST, recovery, and defect tolerance procedures are based on the reconfiguration of the nanofabric to achieve complete fault coverage for different types of faults. We show that a large fraction of defect-free blocks can be recovered using a small number of BIST configurations. We also present simple bounds on the recovery that can be achieved for a given defect density. Simulation results are presented for various nanofabric sizes, different defect densities, and for random and clustered defects. The proposed BIST procedure is well suited for regular and dense architectures that have high defect densities.