NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
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ACM Journal on Emerging Technologies in Computing Systems (JETC)
RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics
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Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics
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Interactive presentation: Improving the fault tolerance of nanometric PLA designs
Proceedings of the conference on Design, automation and test in Europe
CMOS Control Enabled Single-Type FET NASIC
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
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Microelectronics Journal
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IEEE Transactions on Circuits and Systems Part I: Regular Papers
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NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics
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IEEE Transactions on Nanotechnology
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Hardware Viewpoint on Biosequence Analysis: What’s Next?
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Bioinformatics
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Density and regularity are deemed as the major advantages of nanoarray architectures based on nanowires. Literature demonstrated that proper reliability analyzes must be performed and solutions have to be devised to improve nanoarrays yield. Their complexity and high-fault probability claim for specific design automation tools able to explore circuit solutions, performance and fault-tolerant approaches. We envision a simulator conceived to carry on characterizations in terms of logic behavior, defect-induced output error rate assessment, switching activity, power and timing performance. Though already existing for traditional technology, a simulator based on specific technological and topological tiled nanoarray descriptions, and conceived to join both device and architecture levels, has never been attempted at the degree of accuracy we present. Our contribution is twofold. First, marking a difference with respect to the state of the art, we developed an algorithm based on an event-driven engine which works at switch level and is not simply built on top of cost functions evaluations. The straightforward advantage is the possibility to follow the evolution of dynamic control sequences throughout all the inner components of the nanoarray, and, as a consequence, to obtain circuit level characterization as a projection of the real internal parameters. Second, we added to our simulator the capability to inject faults with specific statistical distributions associated to the nanoarray topology. Here we extract output error rates and yield for one of the possible nanoarray structures proposed in literature, the NASIC. Results specificity and accuracy demonstrate the simulator trustworthiness, its effectiveness for extensive nanoarrays characterization and its suitability as a foundation for both higher architectural and lower device simulation levels. The aim of this work, then, is to provide insights into the intertwined relation between actual technology and circuit design for these emerging fabrics, and, as a consequence, to clarify how defects and variability affect circuits and systems performance.