VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A hybrid framework for design and analysis of fault-tolerant architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Nanocomputing in the presence of defects and faults: a survey
Nano, quantum and molecular computing
Tools and techniques for evaluating reliability trade-offs for NANO-architectures
Nano, quantum and molecular computing
Towards an ultra-low-power architecture using single-electron tunneling transistors
Proceedings of the 44th annual Design Automation Conference
A strategy for reliability assessment of future nano-circuits
ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault-tolerant synthesis using non-uniform redundancy
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Fault tolerance design by accurate SER estimation for nano-scale circuits
WSEAS Transactions on Circuits and Systems
History index of correct computation for fault-tolerant nano-computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for enabling fault tolerance in reconfigurable architectures
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Nanoarray architectures multilevel simulation
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
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It is expected that nano-scale devices and interconnections will introduce unprecedented level of defects, noise and interferences in the substrates. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause lack of reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve optimal reliability. Various forms of redundancy such as NAND multiplexing, Triple Modular Redundancy (TMR), Cascaded Triple Modular Redundancy (CTMR) have been considered in the fault-tolerance literature. Also, redundancy has been applied at different levels of granularity, such as gate level, logic block level, logic function level, unit level etc. The questions we try to answer in this paper is what level of granularity and what redundancy levels result in optimal reliability for specific architectures. In this paper, we extend previous work on evaluating reliability-redundancy trade-offs for NAND multiplexing to granularity vs. redundancy vs. reliability trade-offs for other redundancy mechanisms, and present our automation mechanism using the probabilistic model checking tool PRISM. We illustrate the power of this automation by pointing out certain anomalies of these trade-offs which are counter intuitive and can only be obtained by designers through automation, thereby providing better insight into defect-tolerant design decisions.