Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
A study of low level vibrations as a power source for wireless sensor nodes
Computer Communications
SIMON-A simulator for single-electron tunnel devices and circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive simulation for single-electron devices
Proceedings of the conference on Design, automation and test in Europe
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An adaptive algorithm for single-electron device and circuit simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable gate array architecture for logic functions in tunneling transistor technology
Microelectronics Journal
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Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultra-low-power designs may even permit embedded systems to operate without batteries, e.g., by scavenging energy from the environment. Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling. As a result, embedded system price, size, weight, and reliability are all strongly dependent on power dissipation. Recent developments in nanoscale devices open new alternatives for low-power embedded system design. Among these, single-electron tunneling transistors (SETs) hold the promise of achieving the lowest power consumption. However, SETs impose unique design constraints that strongly influence architectural and circuit-level decisions. Unfortunately, most analysis of SETs has focused on single devices instead of architectures, making it difficult to determine whether they are appropriate for low-power embedded systems. This article presents possible uses of SETs in high-performance and battery-powered embedded system design. The resulting fault-tolerant, hybrid SET/CMOS, reconfigurable architecture can be tailored to specific requirements and allows trade-offs among power consumption, performance, operation temperature, fabrication cost, and reliability. This work is a first step in evaluating the system-level potential of reducing power consumption by using SETs.