A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits

Authors:
Santanu Mahapatra;Kaustav Banerjee;Florent Pegeon;Adrian Mihai Ionescu
Affiliations:
Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland;University of California Santa Barbara, CA;Silvaco Data Systems, France;Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland
Venue:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Year:
2003

Citing 2
Cited 1

Few electron devices: towards hybrid CMOS-SET integrated circuits

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Abstract

This paper introduces a CAD framework for co-simulation ofhybrid circuits containing CMOS and SET (Single ElectronTransistor) devices. An improved analytical model for SET is alsoformulated and shown to be applicable in both digital and analogdomains. Particularly, the extension of the recent MIB model forsingle/multi gate symmetric/asymmetric device for a wide range ofdrain to source voltage and temperature is addressed. Circuit levelco-simulations are successfully performed by implementing theSET analytical model in Analog Hardware Description Language(AHDL) of a professional circuit simulator SMARTSPICE.Validation at device and circuit level is carried out by Monte-Carlosimulations. Some novel functionality hybrid CMOS-SETcircuit characteristics: (i) SET neuron (ii) Multiple valued logiccircuit and (iii) a new Negative Differential Resistance (NDR)circuit, are also predicted by the proposed SET model andanalyzed using the new hybrid simulator.