Few electron devices: towards hybrid CMOS-SET integrated circuits

Authors:
Adrian M. Ionescu;Michel J. Declercq;Santanu Mahapatra;Kaustav Banerjee;Jacques Gautier
Affiliations:
Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland;Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland;Swiss Federal Institute of Technology Lausanne, Lausanne, Switzerland;Stanford University, Stanford, CA;CEA-DRT - LETI/DTS - CEA/GRE, Grenoble, France
Venue:
Proceedings of the 39th annual Design Automation Conference
Year:
2002

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Abstract

In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics and functionality of SETs, like unrivalled integration and low power, which are complementary to the sub-20 nm CMOS, are demonstrated. Characteristics of two novel SET architectures, namely, C-SET and R-SET, aimed at logic applications are compared. Finally, it is shown that combination of CMOS and SET in hybrid ICs appears to be attractive in terms of new functionality and performance, together with better integrability for ULSI, especially because of their complementary characteristics. It is envisioned that efforts in terms of compatible fabrication processes, packaging, modeling, electrical characterization, co-design and co-simulation will be needed in the near future to achieve substantial advances in both memory and logic circuit applications based on CMOS-SET hybrid circuits.