Few electron devices: towards hybrid CMOS-SET integrated circuits
Proceedings of the 39th annual Design Automation Conference
Single Electron Tunneling Technology for Neural Networks
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
Silicon Single-Electron Devices and Their Applications
ISMVL '00 Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic
A Linear Threshold Gate Implementation in Single Electron Technology
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
CMOS/nano co-design for crossbar-based molecular electronic systems
IEEE Transactions on Nanotechnology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Interactive presentation: Improving the fault tolerance of nanometric PLA designs
Proceedings of the conference on Design, automation and test in Europe
Cell architecture for nanoelectronic design
Microelectronics Journal
A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density
Proceedings of the 2nd international conference on Nano-Networks
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
On stability of electronic circuits
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Stability analysis of circuits including BJT differential pairs
Microelectronics Journal
Fault-tolerant programmable logic array for nanoelectronics
International Journal of Circuit Theory and Applications
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In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a highly regular, redundant, and scalable design approach based on fixed-weight neural networks and multiple-valued logic are presented. It is demonstrated that the proposed design technique offers significantly improved immunity to permanent and transient faults occurring at the transistor level, and that it results in graceful degradation of circuit performance in response to device failures.