Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
Strategies for nanoelectronics
Microelectronic Engineering - The proceedings of the 2nd international symposium on nano- and giga-challenges in microelectronics
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Towards a framework for designing applications onto hybrid nano/CMOS fabrics
Microelectronics Journal
A Hardware Viewpoint on Biosequence Analysis: What’s Next?
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Bioinformatics
Nanoarray architectures multilevel simulation
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
| Hi-index | 0.00 |
Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric filaments such as Silicon Nano Wires (SiNWs) and Carbon Nano Tubes (CNTs). However, chips leveraging these nanoscale structures are expected to be affected by a large amount of manufacturing faults, way beyond what chip architects have learned to counter. In this paper, we show a design flow, based on software mapping algorithms, to improve the yield of nanometric Programmable Logic Arrays (PLAs). While further improvements to the manufacturing technology will be needed to make these devices fully usable, our flow can significantly shrink the gap between current and desired yield levels. Also, our approach does not need post-fabrication functional analysis and mapping, therefore dramatically cutting on verification costs. We check PLA yields by means of an accurate analyzer after Monte Carlo fault injection. We show that, compared to a baseline policy of wire replication, we achieve equal or better yields (8% over a set of designs) depending on the underlying defect assumptions.