Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics

Authors:
Jie Han;Jianbo Gao;Yan Qi;Pieter Jonker;Jose A. B. Fortes
Affiliations:
University of Florida;University of Florida;Johns Hopkins University;Delft University of Technology;University of Florida
Venue:
IEEE Design & Test
Year:
2005

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Abstract

This article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic. The authors use Markov chain models and bifurcation analysis to compare the degree of redundancy and system reliability in these classical fault-tolerant approaches.