Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
Thermal switching error versus delay tradeoffs in clocked QCA circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LUT-based FPGA technology mapping for reliability
Proceedings of the 47th Design Automation Conference
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In emerging nanotechnologies, reliable computation will have to be carried out with unreliable components being integral parts of computing systems. One promising scheme for designing these systems is von Neumann's multiplexing technique. Using bifurcation theory and its associated geometrical representation, we have studied a NAND-multiplexing system recently proposed. The behavior of the system is characterized by the stationary distribution of a Markov chain, which is uni- or bi-modal, when the error probability of NAND gates is larger or smaller than the threshold value, respectively. The two modes and the median of the stationary distribution are the keys to the characterization of the system reliability. Examples of potential future nanochips are used to illustrate how the NAND-multiplexing technique can lead to high system reliability in spite of large gate error probability while keeping the cost of redundancy moderate. In nanoelectronic systems, while permanent defects can be taken care of by reconfiguration, probabilistic computation schemes can incorporate another level of redundancy so that high tolerance of transient errors may be achieved. The Markov chain model is shown to be a powerful tool for the analysis of multiplexed nanoelectronic systems.