Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems
ITC '04 Proceedings of the International Test Conference on International Test Conference
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Selective Hardening of NanoPLA Circuits
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
IPR: in-place reconfiguration for FPGA fault tolerance?
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Nanotechnology
Using simulation and satisfiability to compute flexibilities in Boolean networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very important at 45nm and beyond. One common defect point is in the lookup table (LUT) configuration bits, which are crucial to the correct operation of FPGAs. In this work we will present an error analysis technique that is able to efficiently calculate the number of critical bits needed to implement each LUT. We will perform this analysis using a scalable overlapping window-based method called DCOW (Don't-care Computation with Overlapping Windows), which allows for accurate and efficient don't-care lower bound calculations. This new windowing technique can approximate the complete don't cares within 2.34%, and can be used for many logic synthesis operations. In particular, we apply DCOW to our FPGA mapping algorithm to reduce the number of possible faults. This will allow the design to have a much higher success of functioning correctly when implemented on a faulty FPGA. By using our algorithm, we are able to reduce the number of possible faults by more than 12% with no area increase.