Online multiple error detection in crossbar nano-architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
LUT-based FPGA technology mapping for reliability
Proceedings of the 47th Design Automation Conference
Online detection of multiple faults in crossbar nano-architectures using dual rail implementations
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Defect-tolerant logic hardening for crossbar-based nanosystems
Proceedings of the Conference on Design, Automation and Test in Europe
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Nanoelectronic components are expected to suffer from very high error rates, implying the need for hardening techniques. We propose a fine-grained approach to harden a promising class of nanoelectronic circuits, called NanoPLAs, against errors. An analytical procedure and simulations are both incorporated into the algorithm to identify the most critical error locations. By targeting errors with the largest impact for a given circuit, the method can provide significant reliability boost at low cost. Furthermore, the method yields a plethora of alternative designs, trading off hardening costs against circuit robustness. In many cases, solutions found achieve both lower cost and higher robustness compared with the duplication-based hardening strategy introduced before.