Markov random field modeling in computer vision
Markov random field modeling in computer vision
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Dynamic programming and the graphical representation of error-correcting codes
IEEE Transactions on Information Theory
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
A probabilistic LDPC-coded fault compensation technique for reliable nanoscale computing
IEEE Transactions on Circuits and Systems II: Express Briefs
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As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this chapter, we exam probabilistic-based design methodologies for designing nanoscale computer architectures based on Markov Random Fields (MRF) The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures. Overall, the probabilistic-based design can dynamically adapt to structural and signal-based faults.