NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Will Moore's Law Be Sufficient?
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
Probabilistic model checking in practice: case studies with PRISM
ACM SIGMETRICS Performance Evaluation Review
The design of DNA self-assembled computing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era
IEEE Design & Test
A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies
IEEE Design & Test
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Nano, quantum, and molecular computing: are we ready for the validation and test challenges?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Fault tolerant nanoelectronic processor architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Test set enrichment using a probabilistic fault model and the theory of output deviations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Nanocomputing in the presence of defects and faults: a survey
Nano, quantum and molecular computing
A probabilistic-based design for nanoscale computation
Nano, quantum and molecular computing
Tools and techniques for evaluating reliability trade-offs for NANO-architectures
Nano, quantum and molecular computing
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards a holistic CAD platform for nanotechnologies
Microelectronics Journal
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
A defect/error-tolerant nanosystem architecture for DSP
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design and implementation of cost-effective probabilistic-based noise-tolerant VLSI circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Defects tolerant logic gates for unreliable future nanotechnologies
IWANN'07 Proceedings of the 9th international work conference on Artificial neural networks
What von Neumann did not say about multiplexing beyond gate failures: the gory details
IWANN'07 Proceedings of the 9th international work conference on Artificial neural networks
Stochastic computational models for accurate reliability evaluation of logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Fault tolerance design by accurate SER estimation for nano-scale circuits
WSEAS Transactions on Circuits and Systems
New Mix codes for multiple bit upsets mitigation in fault-secure memories
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
History index of correct computation for fault-tolerant nano-computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy
Microprocessors & Microsystems
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The shrinking of electronic devices will inevitably introduce a growing number of defects and even make these devices more sensitive to external influences. It is, therefore, likely that the emerging nanometer-scale devices will eventually suffer from more errors than classical silicon devices in large scale integrated circuits. In order to make systems based on nanometer-scale devices reliable, the design of fault-tolerant architectures will be necessary. Initiated by von Neumann, the NAND multiplexing technique, based on a massive duplication of imperfect devices and randomized imperfect interconnects, had been studied in the past using an extreme high degree of redundancy. In this paper, this NAND multiplexing is extended to a rather low degree of redundancy, and the stochastic Markov nature in the heart of the system is discovered and studied, leading to a comprehensive fault-tolerant theory. A system architecture based on NAND multiplexing is investigated by studying the problem of the random background charges in single electron tunneling (SET) circuits. It might be a system solution for an ultra large integration of highly unreliable nanometer-scale devices.