Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Carbon nanotube field-effect transistors and logic circuits
Proceedings of the 39th annual Design Automation Conference
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Defects and Faults in Quantum Cellular Automata at Nano Scale
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study
Journal of Systems Architecture: the EUROMICRO Journal
NanoLab: a nanorobotic system for automated pick-and-place handling and characterization of CNTs
ICRA'09 Proceedings of the 2009 IEEE international conference on Robotics and Automation
Characterization of single-electron tunneling transistors for designing low-power embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
NANOLAB-a tool for evaluating reliability of defect-tolerant nanoarchitectures
IEEE Transactions on Nanotechnology
Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures
IEEE Transactions on Nanotechnology
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As the transistor sizes continue to shrink, quantum effects will significantly affect the circuit behavior. The inherent unreliability of nano-electronics will have significantly impact on the way of circuits design, so defects and faults of nano-scale circuit technologies have to be taken into account early in the design of digital systems. Fault-tolerant architectures may become a necessity to ensure that the underlying circuit could function properly. In CAD software, a same logic can be made out with different circuits but different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the error rate of the circuit efficiently to make the design more fault tolerant. In this paper, a new way to fault tolerance design in nano-scale circuit by accurate soft error rate (SER) estimation is proposed. Transform matrix is used for SER computation and a design criteria is then proposed. Simulation results show that the proposed transform matrix model is effective for nano-scale circuits and the criteria delivered is suitable CAD tools development in nano-system design.