Defect tolerant probabilistic design paradigm for nanotechnologies
Proceedings of the 41st annual Design Automation Conference
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Transduction method for design of logic cell structure
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Nanocomputing in the presence of defects and faults: a survey
Nano, quantum and molecular computing
Proceedings of the 20th annual conference on Integrated circuits and systems design
Numerical study of quantum transport in carbon nanotube transistors
Mathematics and Computers in Simulation
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Analysis of universal logic gates using carbon nanotube field effect transistor
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Fault tolerance design by accurate SER estimation for nano-scale circuits
WSEAS Transactions on Circuits and Systems
A hybrid memory cell using Single-Electron transfer
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Modeling a single electron turnstile in HSPICE
Proceedings of the great lakes symposium on VLSI
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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In this paper, we present recent advances in the understanding of the properties of semiconducting single wall carbon nanotube and in the exploration of their use as field-effect transistors (FETs). Both electrons and holes can be injected in a nanotube transistor by either controlling the metal-nanotube Schottky barriers present at the contacts or simply by doping the bulk of the nanotube. These methods give complementary nanotube FETs that can be integrated together to make inter- and intra-nanotube logic circuits. The device performance and their general characteristics suggest that they can compete with silicon MOSFETs. While this is true when considering simple prototype devices, several issues remain to be explored before a nanotube-based technology is possible. They are also discussed.