The expandable split window paradigm for exploiting fine-grain parallelsim
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
ACM Transactions on Computer Systems (TOCS)
The multicluster architecture: reducing cycle time through partitioning
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Carbon nanotube field-effect transistors and logic circuits
Proceedings of the 39th annual Design Automation Conference
Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Computer
Performance Evaluation of Soft Real-Time Scheduling for Multicomputer Cluster
ICDCS '00 Proceedings of the The 20th International Conference on Distributed Computing Systems ( ICDCS 2000)
Optimizing Static Job Scheduling in a Network of Heterogeneous Computers
ICPP '00 Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Proceedings of the 1st conference on Computing frontiers
Dynamic Scheduling of Parallel Jobs with QoS Demands in Multiclusters and Grids
GRID '04 Proceedings of the 5th IEEE/ACM International Workshop on Grid Computing
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
Measuring the Parallelism Available for Very Long Instruction Word Architectures
IEEE Transactions on Computers
A model for computing and energy dissipation of molecular QCA devices and circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Dynamic redundancy allocation for reliable and high-performance nanocomputing
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
The use of nanoelectronic devices in highly parallel computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures
IEEE Transactions on Nanotechnology
Hierarchical fault tolerance for nanoscale memories
IEEE Transactions on Nanotechnology
Comparing Reliability-Redundancy Tradeoffs for Two von Neumann Multiplexing Architectures
IEEE Transactions on Nanotechnology
Competence research: teaching embedded micro/nano systems
WESE '11 Proceedings of the 6th Workshop on Embedded Systems Education
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Nanoelectronic devices are considered to be the computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that have become a barrier for achieving reliable computing. In addition, transient errors continue to be a problem. The massive parallelism rendered by nanoscale integration opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.