Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A defect/error-tolerant nanosystem architecture for DSP
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Analysis of defect tolerance in molecular crossbar electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper considers dynamic fault tolerance techniques applicable to ultradense memories based on nanoscale crossbar architectures. It describes how they can be integrated, in a hierarchical fashion, to provide runtime protection against device failures. Simulation is employed to estimate the effectiveness of a number of configurations, and the results show that there are synergistic combinations that allow for substantial reliability improvements over conventional techniques. For example, a memory with a bit-level failure rate of 2times10-4 FIT and a failure distribution of 10% arrays and 30% each for bits, rows, and columns shows three orders of magnitude reduction in uncorrectable errors at 100 000 hours when a given amount of redundancy is allocated to a combination of error correction coding and spare rows, columns, and arrays versus other configurations