Carbon nanotube field-effect transistors and logic circuits
Proceedings of the 39th annual Design Automation Conference
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Proceedings of the 1st conference on Computing frontiers
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Fault Secure Encoder and Decoder for Memory Applications
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A model for computing and energy dissipation of molecular QCA devices and circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Prospects for the development of digital CMOL circuits
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
A defect/error-tolerant nanosystem architecture for DSP
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nanowire crossbar logic and standard cell-based integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An information-theoretic analysis of quantum-dot cellular automata for defect tolerance
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
A defect-tolerant memory architecture for molecular electronics
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Hierarchical fault tolerance for nanoscale memories
IEEE Transactions on Nanotechnology
Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories
IEEE Transactions on Nanotechnology
Information Acquisition at the Nanoscale: Fundamental Considerations
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology
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Nano/molecular technologies have emerged as the potential fabrics for building future integrated systems. However, due to the imperfect fabrication process, these extremely scaled devices are vulnerable to a large number of defects and transient faults. Memory systems, which are the primary application targeted by these technologies, are particularly exposed to this problem due to the ultra-high integration density and elevated error sensitivity. In this article, we propose a defect-tolerant technique, referred to as hybrid redundancy allocation, for the design of molecular crossbar memory systems. By using soft redundancy (runtime exploitation of memory spatial/temporal locality) in combination with hardware redundancy (spare memory cells), the proposed technique can achieve better error management at a low cost as compared with conventional techniques. Simulation results demonstrate the significant improvement in defect tolerance, efficiency, and scalability of the proposed technique.