A defect/error-tolerant nanosystem architecture for DSP
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Analysis of defect tolerance in molecular crossbar electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper presents a defect-tolerant memory architecture for molecular electronics. A crossbar structure, where molecules are sandwiched between nanowires, is used as a model to realize molecular memory and to achieve defect tolerance. Defects in the logic circuits for addressing memory are also taken into account. The number of spare rows and columns to form a functioning memory is estimated by computer simulation for various values of defect rate and memory size.