Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays
IEEE Transactions on Computers
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Toward Self-Repairing and Self-Replicating Hardware: The Embryonics Approach
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Highly fault-tolerant parallel computation
FOCS '96 Proceedings of the 37th Annual Symposium on Foundations of Computer Science
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Proceedings of the 1st conference on Computing frontiers
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A Simple High-Speed Multiplier Design
IEEE Transactions on Computers
Application of Self-Configurability for Autonomous, Highly-Localized Self-Regulation
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
A DSP nanosystem with defect tolerance
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
A defect-tolerant memory architecture for molecular electronics
IEEE Transactions on Nanotechnology
Hierarchical fault tolerance for nanoscale memories
IEEE Transactions on Nanotechnology
Run-Time Data-Dependent Defect Tolerance for Hybrid CMOS/Nanodevice Digital Memories
IEEE Transactions on Nanotechnology
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Emerging technologies such as silicon NanoWires (NW) and Carbon NanoTubes (CNT) have shown great potential for building the next generation of computing systems in the nano ranges. However, the excessive number of defects originating from bottom-up fabrication (such as a self-assembly process) poses a pressing challenge for achieving scalable system integration. This article proposes a new nanosystem architecture that employs nanowire crossbars for Digital Signal Processing (DSP) applications. Distributed arithmetic is utilized such that complex signal processing computation can be mapped into regular memory operations, thus making this architecture well suited for implementation by nanowire crossbars. Furthermore, the inherent features of DSP-type computation provide new insights to remedy errors (as logic/computational manifestation of defects). A new defect/error-tolerant technique that exploits algorithmic error compensation is proposed; at system level different trade-offs between correctness in output and performance are established while retaining low overhead in its implementation. As an instance of its application, the proposed approach has been utilized to a generic DSP nanosystem performing frequency-selective filtering. Simulation results show that the proposed nanoDSP introduces only a minor performance degradation under high defect rates and at a range of operational conditions. The proposed technique also features good scalability and viability for various DSP applications.