A DSP nanosystem with defect tolerance

Authors:
Weiguo Tang; Lei Wang
Affiliations:
Department of Electrical and Computer Engineering, University of Connecticut, Storrs, 06269, USA;Department of Electrical and Computer Engineering, University of Connecticut, Storrs, 06269, USA
Venue:
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
Year:
2008

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A defect/error-tolerant nanosystem architecture for DSP

ACM Journal on Emerging Technologies in Computing Systems (JETC)

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Abstract

This paper proposes a new way of employing nanowire (NW) crossbars for digital signal processing (DSP) applications. By employing distributed arithmetic, complicated signal processing tasks can be converted into regular memory operations; thus this architecture is well-suited for NW crossbar technology. A defect-tolerant technique exploiting algorithmic error compensation is proposed to achieve reliable signal processing in the presence of excessive defects. Simulation results show that the DSP nanosystem only introduces minor performance loss under a large range of defect rates and operation conditions. The proposed technique also features good tradeoffs between defect tolerance and the overhead incurred.