Software pioneers: contributions to software engineering
Software pioneers: contributions to software engineering
A multiple bit upset tolerant SRAM memory
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Error Correcting Properties of Redundant Residue Number Systems
IEEE Transactions on Computers
A pageable, defect-tolerant nanoscale memory system
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Challenges in scalable fault tolerance
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Residue-based code for reliable hybrid memories
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Fault secure encoder and decoder for nanomemory applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Hierarchical fault tolerance for nanoscale memories
IEEE Transactions on Nanotechnology
Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories
IEEE Transactions on Nanotechnology
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Hybrid memories are envisioned as one of the alternatives to existing semiconductor memories. Although offering enormous data storage capacity, low power consumption, and reduced fabrication complexity (at least for the memory cell array), such memories are subject to a high degree of intermittent and transient faults leading to reliability issues. This article examines the use of Conventional Redundant Residue Number System (C-RRNS) error correction code, which has been extensively used in digital signal processing and communication, to detect and correct intermittent and transient cluster faults in hybrid memories. It introduces a modified version of C-RRNS, referred to as 6M-RRNS, to realize the aims at lower area overhead and performance penalty. The experimental results show that 6M-RRNS realizes a competitive error correction capability, provides larger data storage capacity, and offers higher decoding performance as compared to C-RRNS and Reed-Solomon (RS) codes. For instance, for 64-bit hybrid memories at 10% fault rate, 6M-RRNS has 98.95% error correction capability, which is 0.35% better than RS and 0.40% less than C-RRNS. Moreover, when considering 1Tbit memory, 6M-RRNS offers 4.35% more data storage capacity than RS and 11.41% more than C-RRNS. Additionally, it decodes up to 5.25 times faster than C-RRNS.