Fault tolerant nano-memory with fault secure encoder and decoder
Proceedings of the 2nd international conference on Nano-Networks
A pageable, defect-tolerant nanoscale memory system
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Hybrid memories, structured from scaled CMOS and non-CMOS devices, are novel memory architectures that offer trillion-capacity of data storage. In spite of that, the reliability of such memories is questionable because of (i) imprecise and immature fabrication processes and (ii) unreliable devices. This paper introduces the concept of Residue Number System (RNS), mainly used in digital signal processing and communication, to the realization of reliable hybrid memories. An error correction code based on RNS to mitigate cluster faults in hybrid memories is proposed; such code is referred to as Six Moduli Redundant Residue Number System (6M-RRNS) code. The experimental results show that 6M-RRNS code can achieve competitive error correction capability as the conventional RRNS (C-RRNS) and Reed-Solomon (RS) codes, yet at lower cost. E.g., for hybrid memories with word size of B=32 bits, the 6M-RRNS code requires 88 bits to encode the data, whereas C-RRNS and RS codes require 106 and 96 bits, respectively. It means that for a fixed memory size and given correction capability, the total data that can be stored when using 6M-RRNS coding is 20.4% and 9.1% larger as compared with C-RRNS and RS, respectively. Moreover, the speed at which 6M-RRNS decodes the data is 5.6 times faster than when using C-RRNS; hence allowing for higher performance.