The psychophysics of texture segmentation
Early vision and beyond
Attention to surfaces: beyond a Cartesian understanding of focal attention
Early vision and beyond
Multibit Correcting Data Interface for Fault-Tolerant Systems
IEEE Transactions on Computers
Proceedings of the 15th symposium on Integrated circuits and systems design
Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
Proceedings of the 1st conference on Computing frontiers
Mitigating soft error failures for multimedia applications by selective data protection
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors
Journal of Electronic Testing: Theory and Applications
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
New Mix codes for multiple bit upsets mitigation in fault-secure memories
Microelectronics Journal
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
SRAMs are used nowadays in almost every electronic product. However, as technology shrinks transistor sizes, single and multiple bit upsets only observable in space applications previously are now reported at ground level. This article presents a high level technique to protect SRAM memories against multiple upsets based on correcting codes. The proposed technique combines Reed Solomon code and Hamming code to assure reliability in presence of multiple bit flips with reduced area and performance penalties. Multiple upsets were randomly injected in various combinations of memory cells to evaluate the robustness of the method. The experiment was emulated in a Virtex FPGA platform. Results show that 100% of the injected double faults and a large amount of multiple faults were corrected by the method.