Modeling the cosmic-ray-induced soft-error rate in integrated circuits: an overview
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Adding error-correcting circuitry to ASIC memory
IEEE Spectrum
Design Challenges of Technology Scaling
IEEE Micro
Multibit Correcting Data Interface for Fault-Tolerant Systems
IEEE Transactions on Computers
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
IDDQ Testing of CMOS Opens: An Experimental Study
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test Experiments
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the 15th symposium on Integrated circuits and systems design
A differential built-in current sensor design for high speed IDDQ testing
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A High-Speed Low-Voltage Built-In Current Sensor
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Software pioneers: contributions to software engineering
Software pioneers: contributions to software engineering
A multiple bit upset tolerant SRAM memory
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Single event transients in combinatorial circuits
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
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In this paper, we propose a diagnose strategy based on built-in current sensors able to detect the effects of single event transients (SETs) in SRAM memory decoders. By analyzing the effects, it is possible to mitigate the error by warning the system about the erroneous write and read operation or by circuit error correction avoiding catastrophic multiple bit upset errors. While EDAC can only protect faults in the memory cell array, the proposed method can cope with faults in the combinational memory circuitry. This BICS-based technique can be used in combination with EDAC to achieve high reliability in memories fabricated in nanometer technologies. Our methodology has been validated by Spice simulation and results show that our approach presents a low area, performance and power dissipation penalty.