An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories

Authors:
Balkaran Gill;Michael Nicolaidis;Francis Wolff;Chris Papachristou;Steven Garverick
Affiliations:
Case Western Reserve University, Cleveland, Ohio;iRoC Technologies, Grenoble, France;Case Western Reserve University, Cleveland, Ohio;Case Western Reserve University, Cleveland, Ohio;Case Western Reserve University, Cleveland, Ohio
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

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Abstract

In this paper we propose a new Built in Current Sensor (BICS) to detect single event upsets in SRAM. The BICS is designed and validated for 100nm process technology. The BICS reliability analysis for process, voltage, temperature, and power supply noise are provided. This BICS detect various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. This BICS found to be very reliable for process, voltage and temperature variation and under stringent noise conditions.